AMD is currently preparing EPYC Milan server processors based on Zen 3 architecture, which will replace the current Zen 2 based EPYC Rome processors. They are currently at the testing stage, and Igor’s Lab has shared information about the specifications of several engineering samples of future AMD server solutions.
We are talking about two samples of the older 64-core models, as well as a sample of the 32-core EPYC Milan. The first are built according to the “8 + 1” scheme, which means the presence of eight crystals (Core Complex Dies, CCD) with Zen 3 cores and one crystal with I / O interfaces. In turn, the 32-core processor is made according to the “4 + 1” scheme – four CCD crystals and an input-output crystal.
The cache volume for new products has not changed compared to its predecessors: for each core there are 32 Kbytes of cache in the first level and 512 Kbytes of cache in the second level, and the total volume of cache in the third level is 256 and 128 MB for the 64- and 32-core processor, respectively. But as AMD itself noted earlier, in Milan the structure of the third-level cache has slightly changed. If the current EPYC Rome every eight-core CCD has two 16 MB cache blocks shared between the four cores, then the future EPYC Milan all 32 MB of the third level cache in the CCD will be common to all eight cores. This will reduce latency and improve performance.
But the most interesting is not the organization of cache memory, but the processor clock speeds. In one of the 64-core samples, the maximum Boost frequency is only 2.2 GHz, while in the other, as well as in the 32-core chip, it is 3.0 GHz. For engineering samples, this is very impressive. Especially when you consider that the serial EPYC Rome maximum Boost frequency reaches 3.4 GHz. This gives hope that ultimately the EPYC Milan processors will be able to offer a fairly noticeable increase in clock speed compared to current AMD server processors.
If you notice an error, select it with the mouse and press CTRL + ENTER.