Although Intel recently released the 10th generation Core Core (S-Lake-S) desktop processors, rumors are circulating on the web not only about their successors to the Rocket Lake-S (11th-generation), but even about 12th-generation chips Alder Lake-S. In particular, not so long ago an unusual arrangement of the latter was reported, implying a combination of “large” and “small” cores. And now these rumors are partly confirmed.
According to previous information leaks, Alder Lake-S processors will contain up to sixteen cores, however, divided into two clusters. One of them will combine eight “large” cores, apparently with the architecture of Willow Cove or its successor. In the other – “small” cores, most likely with the energy-efficient architecture of Tremont or, again, with its successor. By switching between clusters depending on the tasks, Alder Lake-S processors will be able to provide not only high performance, but also better energy efficiency.
New indications of the hybrid structure of Alder Lake-S processors were found in the code for the latest version of the GCC 11 compiler package under GNU (GNU Compiler Collection 11). It is reported that these compilers received support for both the Alder Lake-S desktop processors and the Xeon server generations of Sapphire Rapids, which should replace Ice Lake-SP.
The updated GCC has support for new instructions that will appear in future processors. At the same time, as the Phoronix resource noted, although, on the one hand, Alder Lake desktops support several new instruction sets, on the other hand, they lack quite a few instructions supported by current processors. The most striking example is the complete lack of support for instructions from the AVX-512 set.
This is precisely what points to hybrid architecture. Apparently, support for the AVX-512 in hybrid processors is not possible at this stage, due to the peculiarities of the operating system scheduler working with them. While these sets of vector commands are guaranteed to be supported in both Sunny Cove and Willow Cove, they are not implemented in the “small” kernels of the Tremont class. For this reason, processors where both types of cores are combined do not receive support from the AVX-512. A vivid example here can be the Lakefield hybrid processor, combining the “large” Sunny Cove core with the “small” Tremont, in which the AVX-512 is not supported. From this we can conclude that in Alder Lake there will also be coexisting cores with different architecture: both full-fledged and stripped-down.
According to preliminary data, Alder Lake-S processors will come to the market in early 2022 and will be used in the new LGA 1700 desktop platform, which will support PCIe 4.0 and DDR5 SDRAM. For their production, a 10-nm third-generation manufacturing process will be used.
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