Intel has been developing silicon photonics for 15 years. As in almost everywhere in modern electronics, once it all began with the creation of individual components, which over time became more compact and efficient and increasingly integrated with each other. The company is now ready to move on to the next step, so-called Integrated Photonics, which will embed optical components directly into chips.
A complex for optical data reception and transmission should have several key elements: a light source and its detector, modulating for (de-) multiplexing, a signal carrier and its amplifier, as well as electronic strapping and technology for packaging all this stuff together. All this has long been implemented in the equipment for fiber-optic communication networks – Intel itself has already delivered about 4 million optical transceivers of the 100G class and, for quite some time, promises the appearance of 400G solutions.
But the ultimate goal, as has been repeatedly stated, is the integration of “optics” into “silicon”, that is, the use of optical communication lines inside the server, and not outside it – between its individual components and inside the chips themselves. However, scaling down to this level raises a lot of problems with compactness, power consumption, and proper integration with other semiconductor components. Now for the transition to integrated photonics, according to the company, everything is almost ready – the prototype includes five “pillars” of integrated silicon photonics.
The first of them is ring modulators, which are a thousand times smaller than similar solutions. It is their size that determines the possibility of including them in the composition of chips. They work quite simply: a resonator ring, where light enters, is controlled by electrical impulses and can quickly change its optical properties, freely passing or delaying the light flux. Thus, “zeros” and “ones” are formed that encode the signal. A similar approach is used, for example, in the developments of Imec.
Several such modulators – four, eight, sixteen and more – can be “hung” on one optical fiber, and each of them can be tuned to a certain wavelength. Together they form the familiar WDM scheme. The light source, and these are two more “pillars”, is a semiconductor laser capable of delivering flux simultaneously at four wavelengths, combined with an amplifier made of the same material, which simplifies production and reduces costs.
But here lies one “trick” – the modulator can simultaneously be a photodetector for waves with a length of 1.3-1.6 microns! And, what is very important, it is made of silicon, not germanium or indium – this is another “pillar”. And, see above, this also simplifies and reduces the cost of the production process. The photo detector can already operate at speeds up to 112 Gb / s, although this figure suggests that the upper limit here is not physical in nature, but appears due to other components.
Finally, the last “pillar” is the integration of all components together within the framework of existing technical processes. In particular, in the demonstration of the 100G transceiver, it was mentioned that it consists of two layers located one above the other (3D-packing) and united by copper conductors: the lower one is responsible for photonics and turn on lasers and modulators, and the upper one is a conventional CMOS microcircuit. … The latter is responsible for communication with other chips, and also controls modulators, which are very sensitive to temperature changes.
Why do you need all this? Replacing electrical connections with optical ones will reduce the pins of the chip, while increasing bandwidth and lowering power consumption. At the same time, the electrical connections themselves, in addition to the obvious limitation on the length of the connections, also have a limit in terms of energy efficiency – with the current growth in the speed of connections, the moment is not far off when more energy will be spent on powering communication lines than on actual calculations.
There is already a tendency towards a noticeable increase in the number of contacts in a socket, a significant part of which goes to PCIe and DDR. For the latter, serial interfaces like OMI are offered as an alternative, but PCIe lines are still not enough. Therefore, modern accelerators have acquired dedicated interfaces, for example, NVLink and Infinity Fabric, for direct data exchange with each other.
However, they do not scale well outside the chassis, because again they are limited by the PCIe bus required by the network adapters. DARPA FastNIC program is intended to eliminate the huge difference in the bandwidth of the chips themselves and the networks connecting them. DARPA also has the PIPES program (Photonics in the Package for Extreme Scalability), which is directly aimed at the development of integrated photonics. In particular, Intel and Xilinx participate in it (after the purchase, apparently, AMD already).
As part of its developments in the field of integrated photonics, Intel has so far set relatively modest goals, wanting to achieve 1 Tbit / s bandwidth per fiber, 1 pkJ / bit energy efficiency and communication line lengths up to 1 km. In the long term – getting speeds of tens and hundreds of terabits per second per socket. This will be enough for direct connection of processors and other computing devices directly to each other within an entire data center, which will radically change the approach to collecting, storing, transferring and processing information.