AMD company boldly talks about its approach to the layout of modern processors – it has been using so-called chiplets for several years in a row, and can provide the results of calculations confirming the feasibility of this approach. Interestingly, chiplet processors need more silicon than monolithic ones, but the former are still cheaper to manufacture.
AMD representatives managed to publish the next results of calculations as part of the ISSCC 2021 event, the agenda of which was followed by the EE Times website. A year ago, AMD already explained that a hypothetical 32-core EPYC processor on a monolithic crystal would be twice as expensive as one assembled from chiplets, and the company would not be able to release a model with 64 cores using a monolithic layout at all.
Taking the topic further, AMD reported this year that a 32-core EPYC processor with four chiplets consumes roughly 852mm2 silicon, and its hypothetical analogue with a monolithic crystal would occupy an area of 777 mm2… It would seem that the silicon consumption when using chiplets is about 10% higher, but in practice, a multichip processor turns out to be 41% cheaper to manufacture. First, compact crystals give a lower percentage of rejects, since the risk of concentration of defects on the crystal is reduced. Secondly, the processor can be assembled from dissimilar crystals produced using different lithographic technologies. The most advanced and most expensive technical processes are needed to manufacture crystals with computing cores and other high-speed logic. The auxiliary part can be content with older production technologies, which are cheaper. Nevertheless, the increase in silicon consumption during the transition to chiplets increases the burden on manufacturers and aggravates the shortage of products.
AMD reminds that the release of a conditional crystal with an area of 250 mm2 using 5nm technology is more than four times more expensive than using 45nm technology. A monolithic 7nm EPYC processor with 32 cores would be twice as expensive as a multichip. Well, the increase in silicon consumption by 10% with this arrangement is explained by the appearance of additional logic, which is needed to transfer information between chiplets and coordinate their work. In the future, AMD will think about integrating memory chips on a chip with computational cores, as well as using higher density connection methods. These ideas are known to be shared by Intel to a certain extent.
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