Colossально: ИИ-сервер Graphcore с четырьмя IPU на борту

TSMC and Graphcore create AI platform based on 3nm technology / ServerNews

Despite all the challenges in the semiconductor industry, technology continues to advance. Technological norms of 7 nm are no longer a miracle, more subtle norms, for example, 5 nm, are being mastered with might and main. And the leading contract manufacturer, TSMC, is storming the next peak – the 3nm process technology. One of the first products based on this technology will be the Graphcore AI platform with four next-generation IPUs.

The British company Graphcore has been developing specific accelerators for several years now. Last year, it introduced the IPU (Intelligence Processing Unit) processor, which is interesting in that it does not consist of cores, but of so-called tiles, each of which contains a computing core and some amount of integrated memory. A total of 1216 such tiles provide 300 MB of ultrafast memory with a bandwidth of up to 45 TB / s, and IPU processors communicate with each other via IPU-Link at a speed of 320 GB / s.

Colossal: Graphcore AI server with four IPUs on board

Colossal: Graphcore AI server with four IPUs on board

The company took care of the software maintenance of its brainchild, providing it with the Poplar stack, which provides integration with TensorFlow and Open Neural Network Exchange. Microsoft became interested in the development of Graphcore, using IPU in Azure services, and joint testing showed the most positive results. The next generation IPU, Colossus MK2, presented this summer, turned out to be more complex than NVIDIA A100 and received 900 MB of ultrafast memory.

Machine learning, which is based on training and using neural networks, itself requires processors with a very high degree of parallelism, and this, in turn, automatically means a huge number of transistors – 59.4 billion in the case of the Colossus MK2. Therefore, the development of new, thinner and more economical technical processes is a key task for this class of microchips, and Graphcore understands this, declaring its cooperation with TSMC.

Tiled architecture Graphcore

Tiled architecture Graphcore Colossus MK2

Currently, TSMC is preparing a new technical process with 3 nm standards for the start of “risky” production, and the implementation rate is such that the first products based on it should see the light of day in 2021, and mass production will be launched in the second half of 2022. And one of the first products based on 3nm technology will be Graphcore’s new IPU, now known as N3. Apparently, the British developer is not going to use 5 nm.

The company's plans clearly indicate the use of a 3-nm technical process

The company’s plans clearly indicate the use of a 3-nm technical process

Colossus MK2 chips are currently manufactured using the 7nm process (TSMC N7). They include 1472 tiles and are able to simultaneously execute 8832 threads. In the mode of training neural networks using FP16 calculations, this gives 250 teraflops, but there is a convenient 1 Pflops solution – this is a special 1U Graphcore server, in which four IPUs are supplemented with 450 GB of external memory. PCI Express expansion cards with onboard IPU chips are also available.

Graphcore is doing well, its technology is in demand, and investors include Microsoft, BMW, DeepMind and a number of other companies that develop and implement machine learning complexes. The development of a 3nm chip will further strengthen the position of this developer. Thinner technical processes significantly increase the cost of development, but Graphcore still has financial reserves; at the same time, the option of closer cooperation is not excluded, in which part of the development cost will be borne by TSMC.