two CCDs, one CCX to CCD, 32MB L3 to CCX

two CCDs, one CCX to CCD, 32MB L3 to CCX


Last night, a technical document surfaced on the Web describing some of the characteristics of the expected Ryzen 4000 processors built on the Zen 3 microarchitecture. In general, he did not bring any special revelations, but he confirmed many of the assumptions that were made earlier.

According to the documentation, Ryzen 4000 processors (codenamed Vermeer) will retain the chipset layout introduced in their predecessors of the Zen 2 generation. Future mainstream processors, as before, will have an I / O chiplet and one or two CCD (Core –°omplex Die) chiplets containing computing cores.

The key difference between Zen 3 processors will be the internal structure of the CCD. While currently each CCD contains two quad-core CCX (Core Complex) complexes, each with its own 16MB L3 cache segment, the Ryzen 4000 chiplets will consist of one eight-core CCX. The amount of L3 cache in each CCX will be increased from 16 to 32 MB, but this obviously will not lead to a change in the total capacity of the cache memory. Ryzen 4000 series octa-core processors, which will now have a single CCD chiplet, will have 32MB L3 cache, while 16-core CPUs with two CCD chiplets will have 64MB L3 cache, made up of two segments.

There is no need to wait for changes in the L2 cache size: each of the processor cores will have 512 KB of L2 cache.

However, CCX upscaling will obviously have a performance impact. Each of the cores in Zen 3 will have direct access to a larger portion of the L3 cache, and more cores will be able to communicate directly, bypassing the Infinity Fabric. This means that Zen 3 will reduce inter-core communication delays, and the impact on performance of the limited bandwidth of the connecting part of the processor bus of the Infinity Fabric will decrease, which means, ultimately, the IPC indicator (the number of instructions executed per clock cycle) will increase.

At the same time, we are not talking about any increase in the number of cores in consumer processors. The maximum number of CCD chiplets in the Ryzen 4000 will be limited to two, so the maximum number of cores in the processor will not be able to step over 16.

Also, no major changes with memory support are expected. As follows from the document, the maximum officially supported mode for Ryzen 4000 will remain DDR4-3200.

The documentation does not provide any details about the composition of the lineup and the frequencies of the processors included in it. More details will likely be released on October 8th when AMD is hosting a special event dedicated to Ryzen 4000 processors and Zen 3 microarchitecture.

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